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4-mbit (256k x 16) static ram cy62147dv30 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05340 rev. *f revised august 31, 2006 features ? temperature ranges ? industrial : ?40c to +85c ? automotive-a: ?40c to +85c ? automotive-e: ?40c to +125c ? very high speed: 45 ns ? wide voltage range: 2.20v?3.60v ? pin-compatible with cy62147cv25, cy62147cv30, and cy62147cv33 ? ultra-low active power ? typical active current: 1.5 ma @ f = 1 mhz ? typical active current: 8 ma @ f = f max ? ultra low standby power ? easy memory expansion with ce , and oe features ? automatic power-down when deselected ? cmos for optimum speed/power ? available in pb-free and non pb-free 48-ball vfbga and non pb-free 44-pin tsopii ? byte power-down feature functional description [1] the cy62147dv30 is a high-performance cmos static ram organized as 256k words by 16 bits. this device features ad- vanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down featur e that significantly reduces power consumption. the device can also be put into standby mode reducing power consumption by more than 99% when deselected (ce high or both ble and bhe are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-im- pedance state when: deselected (ce high), outputs are dis- abled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the cy62147dv30 is available in a 48-ball vfbga, 44 pin tsopii packages. note: 1. for best practice recommendations, please refer to the cypres s application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 256k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we ble bhe a 16 a 0 a 1 a 17 a 9 power - down circuit bhe ble ce a 10 [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 2 of 12 notes: 2. nc pins are not internally connected on the die. 3. dnu pins have to be left floating or tied to v ss to ensure proper application. 4. pins h1, g2, and h6 in the vfbga package are address ex pansion pins for 8 mb, 16 mb, and 32 mb, respectively. 5. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. pin configuration [2, 3, 4] vfbga (top view) 44 tsop ii (top view) we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe vss a 7 i/o 0 bhe nc a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16 dnu vcc we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 17 a 16 a 15 a 14 a 4 a 3 oe v ss a 5 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 1 a 0 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 6 a 7 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 8 a 9 a 10 a 11 a 13 a 12 nc product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) range f = 1mhz f = f max min. typ. [5] max. typ. [5] max. typ. [5] max. typ. [5] max. cy62147dv30ll industrial 2.2v 3.0 3.6 45 1.5 3 10 20 2 8 cy62147dv30ll industrial 2.2v 3.0 3.6 55 1.5 3 8 15 2 8 cy62147dv30l auto-e 25 cy62147dv30ll industrial 2.2v 3.0 3.6 70 1.5 3 8 15 2 8 cy62147dv30ll auto-a 8 [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 3 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ......................................?0.3v to + v cc(max) + 0.3v dc voltage applied to outputs in high-z state [6,7] ..........................?0.3v to v cc(max) + 0.3v dc input voltage [6,7] ..................... ?0.3v to v cc(max) + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ ........... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range device range ambient temperature [t a ] [9] v cc cy62147dv30l automotive-e ?40c to +125c 2.20v to 3.60v cy62147dv30ll industrial ?40c to +85c automotive-a ?40c to +85c electrical characteristics (over the operating range) parameter description test conditions ?45 ?55/?70 unit min. typ. [5] max. min. typ. [5] max. v oh output high voltage i oh = ?0.1 ma v cc = 2.20v 2.0 2.0 v i oh = ?1.0 ma v cc = 2.70v 2.4 2.4 v v ol output low voltage i ol = 0.1 ma v cc = 2.20v 0.4 0.4 v i ol = 2.1 ma v cc = 2.70v 0.4 0.4 v v ih input high voltage v cc = 2.2v to 2.7v 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v cc = 2.7v to 3.6v 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage v cc = 2.2v to 2.7v ?0.3 0.6 ?0.3 0.6 v v cc = 2.7v to 3.6v ?0.3 0.8 ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ind?l ?1 +1 ?1 +1 a auto-a [9] ?1 +1 a auto-e [9] ?4 +4 a i oz output leakage current gnd < v o < v cc , output disabled ind?l ?1 +1 ?1 +1 a auto-a [9] ?1 +1 a auto-e [9] ?4 +4 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels 10 20 8 15 ma f = 1 mhz 1.5 3 1.5 3 ma i sb1 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ?0.2v, v in < 0.2v) f = f max (address and data only), f = 0 (oe , we , bhe and ble ), v cc = 3.60v ind?l ll 8 8 a auto-a [9] ll 8 auto-e [9] l25 i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.60v ind?l ll 8 8 a auto-a [9] ll 8 auto-e [9] l25 notes: 6. v il(min.) = ?2.0v for pulse durations less than 20 ns. 7. v ih(max.) = v cc + 0.75v for pulse durations less than 20 ns. 8. full device ac operation assumes a 100- s ramp time from 0 to v cc (min) and 200- s wait time after v cc stabilization. 9. auto-a is available in ?70 and auto-e is available in ?55. [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 4 of 12 notes: 10. tested initially and after any design or proc ess changes that may affect these parameters. 11. test condition for the 45-ns part is a load capacitance of 30 pf. 12. full device operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. 13. bhe .ble is the and of both bhe and ble . chip can be deselected by either disabling the chip enable signals or by disabling both bhe and ble . capacitance (for all packages) [10] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance [10] parameter description test conditions vfbga tsop ii unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 72 75.13 c/w jc thermal resistance (junction to case) 8.86 8.95 c/w ac test loads and waveforms [10] parameters 2.50v 3.0v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min. typ. [5] max. unit v dr v cc for data retention 1.5 v i ccdr data retention current v cc = 1.5v ce > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v l (auto-e) 15 a ll (ind?l/auto-a) 6 t cdr [10] chip deselect to data retention time 0 ns t r [12] operation recovery time t rc ns v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 data retention waveform [13] v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r v cc ce or bhe .ble [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 5 of 12 switching characteristics over the operating range [14] parameter description 45 ns [11] 55 ns 70 ns unit min. max. min. max. min. max. read cycle t rc read cycle time 45 55 70 ns t aa address to data valid 45 55 70 ns t oha data hold from address change 10 10 10 ns t ace ce low to data valid 45 55 70 ns t doe oe low to data valid 25 25 35 ns t lzoe oe low to low z [15] 5 5 5 ns t hzoe oe high to high z [15, 16] 15 20 25 ns t lzce ce low to low z [15] 10 10 10 ns t hzce ce high to high z [15, 16] 20 20 25 ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 45 55 70 ns t dbe ble /bhe low to data valid 45 55 70 ns t lzbe ble /bhe low to low z [15] 10 10 10 ns t hzbe ble /bhe high to high z [15, 16] 15 20 25 ns write cycle [17] t wc write cycle time 45 55 70 ns t sce ce low to write end 40 40 60 ns t aw address set-up to write end 40 40 60 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 35 40 45 ns t bw ble /bhe low to write end 40 40 60 ns t sd data set-up to write end 25 25 30 ns t hd data hold from write end 0 0 0 ns t hzwe we low to high-z [15, 16] 15 20 25 ns t lzwe we high to low-z [15] 10 10 10 ns notes: 14. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 v/ns) or less, t iming reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 15. at any given temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 16. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high impedence state. 17. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write. [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 6 of 12 switching waveforms read cycle 1 (address transition controlled) [18, 19] read cycle no. 2 (oe controlled) [19, 20] notes: 18. the device is contin uously selected. oe , ce = v il , bhe and/or ble = v il . 19. we is high for read cycle. 20. address valid prior to or coincident with ce and bhe , ble transition low. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t lzbe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current t hzbe bhe /ble t lzoe address t dbe t doe [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 7 of 12 write cycle no. 1 (we controlled) [17, 21, 22] write cycle no. 2 (ce controlled) [17, 21, 22] notes: 21. data i/o is high impedance if oe = v ih . 22. if ce goes high simultaneously with we = v ih , the output remains in a high-impedance state. 23. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in note 23 bhe /ble t bw t sce t hd t sd t pwe t ha t aw t sce t wc t hzoe data in ce address we data i/o oe note 23 bhe /ble t bw t sa [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 8 of 12 write cycle no. 3 (we controlled, oe low) [22] write cycle no. 4 (bhe /ble controlled, oe low) [22] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 23 t bw bhe /ble data i/o address t sd t sa t ha t aw t wc ce we data in note 23 t bw bhe /ble t sce t pwe t hzwe t hd t lzwe [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 9 of 12 truth table ce we oe bhe ble inputs/outputs mode power h x x x x high z deselect/power-down standby (i sb ) x x x h h high z deselect/power-down standby (i sb ) l h l l l data out (i/o o ?i/o 15 ) read active (i cc ) l h l h l data out (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o o ?i/o 15 ) write active (i cc ) l l x h l data in (i/o o ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 45 cy62147dv30ll-45bvxi 51-85150 48-ball (6 mm 8mm 1 mm) vfbga (pb-free) industrial cy62147dv30ll-45zsxi 51-85087 44-pin tsop ii (pb-free) 55 cy62147dv30ll-55bvi 51-85150 48-ball (6 mm 8mm 1 mm) vfbga industrial cy62147dv30ll-55bvxi 48- ball (6 mm 8mm 1 mm) vfbga (pb-free) cy62147dv30ll-55zsxi 51-85087 44-pin tsop ii (pb-free) CY62147DV30L-55BVXE 51-85150 48-ball (6 mm 8mm 1 mm) vfbga (pb-free) automotive-e cy62147dv30l-55zsxe 51-85087 44-pin tsop ii (pb-free) 70 cy62147dv30ll-70bvi 51-85150 48-ball (6 mm 8mm 1 mm) vfbga industrial cy62147dv30ll-70bvxa 48-ball (6 mm 8mm 1 mm) vfbga (pb-free) automotive-a [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 10 of 12 package diagram a 1 a1 corner 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 48-ball vfbga (6 x 8 x 1 mm) (51-85150) 51-85150-*d [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 11 of 12 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark, and more battery life is a tra demark, of cypress semiconducto r corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagram (continued) 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy62147dv30 document #: 38-05340 rev. *f page 12 of 12 document history page document title:cy62147dv30 mobl ? 4-mbit (256k x 16) static ram document number: 38-05340 rev. ecn no. issue date orig. of change description of change ** 127481 06/17/03 hrt new data sheet *a 131010 01/23/04 cbd changed from advance to preliminary *b 213252 see ecn aju changed from preliminary to final added 70 ns speed bin modified footnote 7 to include ramp time and wait time modified input and output capacitance values to 10 pf modified thermal resistance values on page 4 added ?byte power-down feature? in the features section modified ordering information for pb-free parts *c 257349 see ecn pci modified ordering information for 70-ns speed bin *d 316039 see ecn pci added 45-ns speed bin in ac, dc and ordering information tables added footnote #10 on page #4 added pb-free package ordering information on page # 9 changed 44-lead tsop-ii package name on page 11 from z44 to zs44 standardized icc values across ?l? and ?ll? bins *e 330365 see ecn aju added automotive product information *f 498575 see ecn nxr added automotive-a range added note# 9 on page# 3 updated ordering information table [+] feedback [+] feedback

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